ECE 470 Final: ECE470 Oakland Solutions Final Exam
15 Feb 2019
School
Department
Course
Professor
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-470/570: Microprocessor-Based System Design Fall 2014
1 Instructor: Daniel Llamocca
Solutions - Final Exam
(December 9th @ 7:00 pm)
Clarity is very important! Show your procedure!
PROBLEM 1 (15 PTS)
Determine whether the following statements are True or False. If the statement is False, explain why.
HCS12D SCI1: With E-clock = 24 MHz, it is possible for the frequency of the receiver clock to be 2560 Hz.
FALSE.
. Since 2560 < 2930.0451 Hz, SBR requires more than 13 bits.
CAN: The Bit Rate of System A is identical to that of System B. The CAN Bit Time of System A is 8 time quanta, and the
CAN Bit Time of System B is 10 time quanta. Thus, the CAN Bit Time (in units of time) of System A is different to that of
System B.
FALSE. If the Bit Rate of two systems is the same, the CAN Bit Time (in units of time) is the same:
The Real-Time Interrupt can be disabled by setting bit I of CCR to ‘1’.
TRUE
HCS12D CAN: Hard Synchronization takes place at the beginning of the frame, when the start of frame bit changes the
state of the bus from dominant (0) to recessive (1).
FALSE. The start of frame bit changes the state of the bus from recessive (1) to dominant (0).
/XIRQ Interrupt: A user can always disable it at any time during program execution by setting bit X of CCR to ‘1’.
FALSE. Once the /XIRQ is enabled, the user program cannot disable it.
HCS12D SCI1: The receiver clock is 16 times faster than the transmitter clock to allow for synchronization.
TRUE
Complete:
HCS12D ATD0, VDD = 5v: The minimum number of bits that makes sure that the average quantization error never exceeds
0.001v is _12_____.
Average Quantization error: This is the voltage of 1/2 LSB:
Minimum n = 12.
HCS12D Timer with E-clock= 24 MHz and pre-scale factor 8: A count from 0 to the maximum count lasts _21.8453_ ms
. A count takes:
.
HCS12D SPI0: If E-clock = 24 MHz and SPI0BR = 0x57, the Baud Rate is __15625_____ Hz.
Miscellaneous questions:
PWM signal generation: Mention one advantage of using the PWM Module instead of the Output Compare function?
A PWM signal generated with the Output Compare function either requires continuous attention by the processor or
requires an Interrupt. The PWM requires neither, and allows for more efficient coding.
CAN: What is bit stuffing?
It is a procedure applied by the Transmitter: every 5 consecutive identical bits, a complemented bit is included.
HCS12 Timer: Briefly describe the Input Capture function.
Whenever an event is present on an Input Capture pin, the value of the Timer Counter (TCNT) is loaded on the respective
Input Capture Register.
When servicing an Interrupt, the HCS12 stores PC and CPU registers in the Stack. What information does the PC register
contain?
The PC (Program Counter) contains the Return Address, i.e., the address of the instruction immediately following the
instruction at which the Interrupt was issued.
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-470/570: Microprocessor-Based System Design Fall 2014
2 Instructor: Daniel Llamocca
Mark the correct option:
At power-on, the /IRQ Interrupt is: Disabled Enabled
HCS12D: Which of these two can be modified by the user? Interrupt Vector Vector Address
PROBLEM 2 (10 PTS)
HCS12D – SCI1: Complete the table. E-clock = 24 MHz.
Baud Rate = Tx clock frequency (Hz)
Rx clock frequency (Hz)
SCI1BDH
SCI1BDL
2000
32000
02
EE
The figure below depicts the process of detection of a Start Bit. Using the parameters above, determine the period of the
clock signal in the figure below.
The clock signal is the Receiver clock. Thus, its period is
PROBLEM 3 (20 PTS)
(10 pts) HCS12D Timer: A program measures the period of a signal by using the Input Capture function and reading the
TCNT values of two consecutive edges. In particular, the following values were read: 2017 and 5409.
The program also records the number of Timer overflows (rolling from $FFFF to $0000). In this particular case, the Timer
overflows 3 times between t1 and t2.
What is the frequency of the signal? E-clock = 24 MHz, Timer Pre-scale Factor = 4.
t
??
START BIT
...
t1
216-1
TCNT
t2
216-t1t2
2017
...
0
0
5409
