CMPT 295 Lecture Notes - Lecture 8: Exclusive Or, Bitwise Operation
8 Oct 2016
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An overflow occurs when the result of a computation falls out of range, i. e. makes no sense. Addition: [0, 2n-1] + [0, 2n-1] = [0, 2n+1-2] Overflow if 2n, i. e. if carry-out of most significant bit (msb) is 1. Overflow if less than 0, i. e. if carry-out of msb is 0. Subtraction: [0, 2n-1] - [0, 2n-1] = [-2n+1, 2n-1] 2"s complement addition: [-2n-1, 2n-1-1] + [-2n-1, 2n-1-1] = [-2n, 2n-2] Overflow is sign changed unexpectedly e. g. (-100) + (-100) ~ too negative! In 2"s complement overflow occurred if and only if the carry-in to the msb differs from the carry-out of the msb. Several single-bit registers describing attributes of the most recent arithmetic operation. Cf: carry flag - last operation caused an unsigned overflow. Zf: zero flag - last operation resulted in zero. Sf: sign flag - last operation yielded a negative value. Of: overflow flag - last operation caused a 2"s complement overflow.
