ENVS 1000 Lecture Notes - Lecture 7: Execution Unit
10 May 2018
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ENVS 1000 Tutorial 7 Notes – Multiple, parallel execution units
Introduction
• Pipelining and instruction reordering complicate the electronic circuitry required for the
computer.
• Also require careful design to eliminate the possibility of errors occurring under unusual
sequences of instructions.
• Remember that the programmer must always be able to assume that instructions are
executed in the specified order.
• Despite the added complexity, these methods are now generally accepted as a means
for meeting the demand for more and more computer power.
• The additional task of analyzing, managing, and steering instructions to the proper
execution unit at the proper time is usually combined with instruction fetching and
decoding to form a single instruction unit that handles all preparation of instructions for
execution.
• A diagram illustrating pipelining is shown in Figure 8.5. For simplicity, instruction
reordering has not been included.
• The figure shows three instructions, one for each row in the diagram.
• The steps i the diaga epeset the seuece of steps i the fetch-execute cycle
for each instruction.
• Timing marks are indicated along the horizontal axis.
• The F-E cycle for instruction 3 shows a delay between step 1 and step 2
• Such a delay might result because the second step of the instruction needs a result from
step 3 of the previous instruction, for example, the data in a particular register.
• It is not useful to pipe different types of instructions through a single pipeline.
• Different instructions have different numbers of steps in their cycles and, also, there are
differences in each step.
• Instead, the instruction decodes unit steers instructions into specific execution units.
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