COMPSCI 61C Lecture Notes - Lecture 18: Datapath, Instruction Set, Program Counter
28 Aug 2017
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Document Summary
Our design is for the single cycle datapath. During one clock period, all the tasks necessary for an instruction to complete lw. Sdf | if | id | ex | mem | wb. Stage 1: analyze instruction set to determine datapath requirements. Meaning of each instruction given by register transfers. Datapath must include storage element for isa registers. Stage 2: select set of datapath componenets & establish clock methodology. Stage 3: assemble datapath components that meet the requirements. Stage 4: analyze implementation of each instruction to determine setting of control points that realizes the register transfer. Memory (mem): instructions & data; will use one for each. Add / sub / or / etc unit for operation on register(s) or extended immediate (alu) Add 4 (and maybe extended immediate) to pc. Alu needs for mips-lite and rest of mips. Test to see if output == 0 for any alu operation gives == test.
