ESE 382 Lecture Notes - Lecture 1: Register-Transfer Level, Netlist, Vhdl

• School: Stony Brook University
• Department: Electrical Engineering
• Course: ESE 382
• Professor: Kenneth Short

Document Summary

A gate-level logic implementation is sometimes referred to as a register transfer level (rtl) implementation. This level describes the logic in terms of registers and the boolean equations for the combinational logic between the registers. Of course, for a combinational system there are no registers and the rtl logic consists only of combinational logic. A synthesizer may include its own compiler to compile a design description into the intermediate form used by the synthesizer. This compiler can highlight synthesis errors in the source code. Not all vhdl language constructs can be synthesized. Some synthesis errors result from the use of constructs that can"t be synthesized. Typically, a synthesizer performs three steps during synthesis: language synthesis: the design description is transformed into a representation based on. These equations represent the interconnection of generic logic elements or functional blocks: optimization: algorithms apply the rules of boolean algebra to optimize the logic for area and/or speed.