CSCE 2214 Lecture Notes - Lecture 7: Vhdl
17 Sep 2016
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Lec 7 9-9-16 vhdl review / data objects / data types. A constant can have a single value of a certain type and can"t be changed. When they are declared at the beginning of an architecture they can be used anywhere within the architecture. When they are declared within a process they can only be used inside that specific process. Variables can be updated using a variable assignment statement. The variables will be local to the process. Must be declared inside the architecture and outside the process. Will be updated when the signal assignment statement is executed signal_name <= expression; They can also be declared as such: signal list_of_signal_names: type [ := initial value] ; Lecture notes page 1 signal list_of_signal_names: type [ := initial value] ; signal sum, carry: std_logic; signal clock: bit; signal trigger: integer :=0; signal data_bus: bit_vector (0 to 7); signal value: integer range 0 to 100; Initializing the signals that represent wires is not necessary.
