CSCI 322 Lecture Notes - Lecture 1: Instrumental Case
11 Jan 2017
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Increase stage duration -> balance the pipeline. Restructure code to reduce stalls (1<2<3 beccomes 1<3<2) Answer: depends on how many intructions and what else is running in the background. No, there are stalls based on previous instructions. Both throughput and latency are governed by the slowest stage. # of instr. per ns is used to compare pipelines. Stalls come about through structural hazards - what we"ve been talking about. There are also data hazards - data dependencies e. g. 1: a=b+c. 1<3<2 7 clock cycles or 1<2<3 7 clock cycles. 1 and 3 don"t stall; 2 stalls for 1 clock cycle.
