FIT1047 Study Guide - Final Guide: Register Transfer Language, Master Boot Record
31 May 2018
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Instructions to Circuits
Data Paths
• Describes how the different functional units, in particular the registers and the ALU are
connected.
• Hardware implementation of the data paths is the system bus (set of wires that connect all
components)
Register Transfer Language (RTL)
Fetch:
1. MAR <--- PC
2. MBR <--- M[MAR]
3. IR <---- MBR
4. PC <---- PC + 1
Decode:
5. MAR <---- X
6. MBR <---- M[MAR]
Fetch:
LOAD X:
7. AC <---- MBR
STORE X:
6. MBR <---- AC
7. M[MAR] <---- MBR
ADD X:
7. AC <---- AC + MBR
SUBT X:
7. AC <---- AC - MBR
SkipCond X:
6. If MAR = 0x800 and AC > 0 then PC <--- PC + 1
6. If MAR = 0x400 and AC = 0 then PC <---- PC + 1
6. If MAR = 0x000 and AC < = then PC <---- PC + 1
JUMP X:
6. PC <----- MAR
Clear:
5. AC <---- 0
ADDI X:
7. MAR <----- MBR
8. MBR <---- M[MAR]
9. AC <---- AC + MBR
JUMPI X:
7. PC <---- MBR
LOADI X:
7. MAR <----- MBR
8. MBR <---- M[MAR]
9. AC <---- MBR
STOREI X:
7. MAR <----- MBR
8. MBR <---- AC
9. M[MAR] <---- MBR
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