ECE327 Final: ECE 327 University of Waterloo 2013 Term 1 Final
31 Jan 2019
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Calculators are allowed: the proctors and instructors will not answer questions, except in cases where an error on the exam is suspected. If you are confused about a question, write down your assumptions or interpretation: justi cations of answers will be marked according to correctness, clarity, and concision. 2 (a c v2 f) + ( a v ish f) + (v il) Q1 (10 marks) simulation (estimated time: 5 minutes) Q2 (10 marks) area analysis (estimated time: 10 minutes) Calculate the mininum number of fpga cells needed to implement the vhdl code below. Notes: the signal a is std logic, the signals b, c, d, e, and z are 12-bit unsigned, each fpga cell has a 4:1 lut with carry-in and carry-out signals, and a 1-bit register. Q3 (10 marks) pipelining (estimated time: 15 minutes) In this question, you will optimize the data ow diagram below. First, try to nd an optimization that satis es option 1 below.
