ECE327 Final: ECE 327 University of Waterloo 2014 Term 1 Final Solution

• School: University of Waterloo
• Department: Electrical and Computer Engineering
• Course: ECE327
• Professor: All

Document Summary

Q1 (5 marks) simulation (estimated time: 7 minutes) Describe where in the simulation algorithm a problem will rst occur and describe what the problem will be. Circuits with combinational loops are not supported by register-transfer-level simulation. The problem will occur when the register-transfer-level simulation algorithm attempts to do a topological sort of the decomposed combinational processes. The processes in the combinational loop do not have a topological order. The sorting algorithm will either get stuck in an in nite loop or will detect the loop and fail. +1 mark can"t topo sort, or get stuck in in nite loop (page 2 of 20) Q2 (10 marks) retiming (estimated time: 18 minutes) Use retiming to modify the circuit below without changing the behaviour of the output z. 13 g h z (page 3 of 20) +1 mark no ops on a, b, c. +1 marks exactly 1 op on e, g loop.