ECE327 Midterm: ECE 327 University of Waterloo 2016 Term 1 Midterm Solution

• School: University of Waterloo
• Department: Electrical and Computer Engineering
• Course: ECE327
• Professor: All

Document Summary

All requests for re-marks must be submitted in writing to mark aagaard before 8:30am on friday march 11. Exams that are submitted for re-marking will be veri ed against this set. Q1 (25 marks) vhdl semantics (estimated time: 15 minutes) For the vhdl program below, calculate the values for the signals c, d, e, and f at 15ns. You may, but are not required to, show a delta-cycle simulation. process begin clk1 <= "0"; wait for 10 ns; clk1 <= "1"; wait for 10 ns; end process; process begin. 200; a <= (others => "0"); wait for 10 ns; a <= a + <= a; process begin wait until rising_edge( clk1 ); c <= a; d <= b; end process; process begin wait until rising_edge( clk2 ); e <= a; f <= b; end process; (page 2 of 11) The schematic is not a necessary part of the answer. a clk1. 15ns clk1 clk2 a b c d e f.