ECE327 Midterm: ECE 327 University of Waterloo 2016 Term 2 Midterm Solution

• School: University of Waterloo
• Department: Electrical and Computer Engineering
• Course: ECE327
• Professor: All

Document Summary

All requests for re-marks must be submitted in writing to mark aagaard before noon on thursday june 30. Exams that are submitted for re-marking will be veri ed against this set. Q1 (25 marks) vhdl (estimated time: 15 minutes) On the rst day of your dream co-op job at amabagookify, the company goes bankrupt and you lose your job. You decide to create a startup company based on your idea for a new hardware description language, why wait? , abbreviated as yw . To get the company going quickly, you decide to base yw on vhdl, but eliminate wait statements and sensitivity lists, because they are too complicated. Without at least one timed process, we can"t have a clock or other external inputs that change value. So far, you have decided that in each simulation cycle: each process is executed exactly once, the processes are executed in the order in which they appear in the architecture.