ECE327 Midterm: ECE 327 University of Waterloo 2018 Term 1 Midterm Solution

• School: University of Waterloo
• Department: Electrical and Computer Engineering
• Course: ECE327
• Professor: All

Document Summary

All requests for re-marks must be submitted by email to mark aagaard before noon on friday march 2. Q1 (20 marks) vhdl semantics (estimated time: 10 minutes) At the beginning of the next simulation cycle. 1 mark registered: next clock cycle, comb: immediately. Over the past few years, you have been very successful at creating new hardware description languages that are variations of vhdl (syn opsys, why wait, etc. ). You have earned billions of dollars and are now retired, living on your own tropical island. Despite your luxurious life of leisure, you still have the urge to explore new hardware description languages. All programs will have the same behaviour in vhdl and idle. This solution is longer than necessary for an exam answer. The behaviour of a program in vhdl and idle will be identical, except that the rst simulation step in a simulation cycle in vhdl will become the last simulation step in the previous simulation cycle in.