EECE 252 Study Guide - Verilog
Document Summary
Ledg : out std_logic_vector( 7 downto 0 ); --- component from the verilog file: clock : in std_logic; colour : in std_logic_vector(2 downto 0); x : in std_logic_vector(7 downto 0); y : in std_logic_vector(6 downto 0); plot : in std_logic; Vga_r, vga_g, vga_b : out std_logic_vector(9 downto 0); Vga_hs, vga_vs, vga_blank, vga_sync, vga_clk : out std_logic); Clock_50 : in std_logic; library ieee; use ieee. std_logic_1164. all; use ieee. std_logic_unsigned. all; use ieee. std_logic_arith. all; -signal x_set : std_logic_vector( 7 downto 0 ); -signal y_set : std_logic_vector( 6 downto 0 ); signal colour : std_logic_vector(2 downto 0); signal plot : std_logic; signal slowclk : std_logic; resetn <= key(3); Ledg(0) <= slowclk; vga_u0 : vga_adapter generic map(resolution => 160x120) --- sets the resolution of display (as per clock => clock_50, colour => colour, x => x, y => y, plot => plot, Vga_clk => vga_clk); begin vga_adapter. v description) port map(resetn => resetn,
