ECE 210 Study Guide - Midterm Guide: Councillor, Circuit Diagram, Maurice Karnaugh
23 May 2018
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ECE 210: Logic Design TEST 3
NAME: __________________________
Show all your work. Do your own work; cheating will result in immediate failure.
NOTE: The use of calculators is not allowed.
Problem 1
The D flip-flop below have asynchronous clear and preset inputs. CLR sets Q to logic 0 and SET sets the value of
Q to logic 1.
a. Draw the state table of the flip-flop [10]
b. Draw the timing diagram for Q based on the waveforms shown for SET, D and CLR. Assume no delays.
[15]
Clearly show any unknown states.
Problem 2
a. Draw a state diagram for the following state table with input x and output z: [12]
Q1Q2
Q1* Q2*,z
x=0
x=1
00
00,0
10,1
01
00,0
00,0
10
11,1
01,1
11
10,1
10,0
b. Complete the timing trace as far as possible for the input trace shown. [13]
x
0
1
0
0
1
1
1
0
Q1
0
Q2
0
z
Document Summary
Do your own work; cheating will result in immediate failure. Note: the use of calculators is not allowed. The d flip-flop below have asynchronous clear and preset inputs. Clr sets q to logic 0 and set sets the value of. Q to logic 1: draw the state table of the flip-flop. [10: draw the timing diagram for q based on the waveforms shown for set, d and clr. Problem 2: draw a state diagram for the following state table with input x and output z: 11: complete the timing trace as far as possible for the input trace shown. For the following circuit: what sequential state machine model is shown, write the excitation and transition equations for the two flip-flops and the equation for the output. Call the states 00, 01, 10, 11: explain the function that is performed by this circuit. Design a system for the state table and state assignments shown below.
