E E 319K Final: EE319K FinalF14Sol
EE319K Fall 2014 Final Exam Solutions Page 1
Erez, Valvano, Yerraballi Dec 11, 2014 2:00pm-5:00pm
Final Exam
Date: Dec 11, 2014
UT EID: Circle one: ME, JV, RY
Printed Name:
Last, First
Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat
on this exam. You will not reveal the contents of this exam to others who are taking the makeup thereby giving them an
undue advantage:
Signature:
Instructions:
• Closed book and closed notes. No books, no papers, no data sheets (other than the last four pages of this Exam)
• No devices other than pencil, pen, eraser (no calculators, no electronic devices), please turn cell phones off.
• Please be sure that your answers to all questions (and all supporting work that is required) are contained in the
space (boxes) provided. Anything outside the boxes will be ignored in grading.
• You have 180 minutes, so allocate your time accordingly.
• For all questions, unless otherwise stated, find the most efficient (time, resources) solution.
• Unless otherwise stated, make all I/O accesses friendly.
• Please read the entire exam before starting. See supplement pages for Device I/O registers.
Problem 1 20
Problem 2 10
Problem 3 10
Problem 4 10
Problem 5 10
Problem 6 10
Problem 7 20
Problem 8 10
Total 100
EE319K Fall 2014 Final Exam Solutions Page 2
Erez, Valvano, Yerraballi Dec 11, 2014 2:00pm-5:00pm
(20) Question 1 (Miscellaneous)
(3) Part a) If an Interrupt Service Routine modifies register R0, the ISR does not have to save and
restore R0, why?
R0,R1,R2,R3,R12,LR,PC,PSW are automatically pushed on the stack when the interrupt occurs and
restored by the BX LR at the end of the ISR
(5) Part b) A DAC is used to output a sine wave using SysTick Interrupts and a sine-wave table.
Assume the DAC has 7 bits, the DAC output is connected to a speaker, the SysTick ISR executes at
32kHz, the sine table has 256 elements, and one DAC output occurs each interrupt. The DAC output
range is 0 to 3.3V. The bus clock is 80 MHz. The ADC maximum rate is 125 kHz. What frequency
sound is produced, in Hz?
One output occurs each SysTick ISR, so the sine wave output will be 32kHz/256 = 125 Hz.
(3) Part c) A DAC has a range of 0 to 3V and needs a resolution of 1mV. How many bits are
required? In other words, what is the smallest number of DAC bits that would satisfy the requirements?
precision is (3-0)/0.001 = 3000 alternatives. 11 bits would only be 2048 alternatives, so we need to use
12 bits to get 4096 alternatives.
(3) Part d) An embedded system will use an ADC to capture electrocardiogram (EKG) data. The
frequency range of the human EKG spans from 0.1 Hz to 100 Hz. What is the slowest rate at which we
could sample the ADC and still have a faithful representation of the EKG in the digital samples? Give
your answer as the time between samples.
Nyquist Theorem says sampling rate needs to be larger than 2*fmax, so fs > 200 Hz, which means the
time between samples must be less than 1/200 = 5ms.
(3) Part e) An 8-bit ADC (different from the TM4C123) has an input range of 0 to +10 volts and an
output range of 0 to 255. What digital value will be returned when an input of +7.5 volts is sampled?
Give your answer as a decimal number.
256*7.5/10 = 192 or 255*7.5/10 = 191
(3) Part f) A serial port (UART1) is configured with one start, 8 data bits, one stop and a baud rate of
50,000 bits/sec. What is the maximum possible bandwidth of this port in bytes/sec?
50,000 bits/sec (8 bits data/10 bits in frame)*(1byte/8bits) = 5,000 bytes/sec
EE319K Fall 2014 Final Exam Solutions Page 3
Erez, Valvano, Yerraballi Dec 11, 2014 2:00pm-5:00pm
(10) Question 2 (FSM). You will design a pacemaker using a Moore FSM. There is one input and one
output. The input will be high if the heart is beating on its own. The input will be low if the heart is not
beating on its own. If the heart is not beating your machine should pace the heart. If the heart is beating
on its own, the input will be high and your output should be low. However, if the input is low, you
should pace the heart by giving a 10 ms output pulse every 1 sec. PB0 is output, PB1 is input.
(5) Part a) Show the FSM graph in Moore format. Full credit for the solution with the fewest states.
Two good answers
Pace must be 10ms, but the other two can be any times that add to 990ms
(5) Part b) The structure and the main program is fixed. Show the C code that places the FSM in
ROM, and specify the initial state in the box.
const struct State{
uint32_t out;
uint32_t wait;
uint32_t next[2];
};
typedef const struct State State_t;
uint32_t s;
#define Check 0
#define PaceIt 1
STyp FSM[2]={
{0, 990, { Wait, Check}},
{1, 10, { PaceIt, Check}}};
void main(void){ PORTB_Init();
SysTick_Init();
s = ;
while(1){
GPIO_PORTB_DATA_R = FSM[s].out;
SysTick_Wait1ms(FSM[s].wait);
Input =
(GPIO_PORTB_DATA_R&0x02)>>1;
s = FSM[s].next[Input];
}}
#define Beating 0
#define Wait 1
#define Pace 2
STyp FSM[3]={
{0, 10, { Wait, Beating}},
{0, 980, { Pace, Beating}},
{1, 10, {Beating, Beating}}};
Input
Output
exactly 10ms
exactly 1s
exactly 10ms
about 1s
Init
Check
990ms
0
1
PaceIt
10ms
1
0,1
0
Check
Init
Beating
10ms
0
1
Wait
980ms
0
1
0
Pace
10ms
1
0,1
0
Document Summary
Your signature is your promise that you have not cheated and will not cheat on this exam, nor will you help others to cheat on this exam. You will not reveal the contents of this exam to others who are taking the makeup thereby giving them an undue advantage: Assume the dac has 7 bits, the dac output is connected to a speaker, the systick isr executes at. 32khz, the sine table has 256 elements, and one dac output occurs each interrupt. The dac output range is 0 to 3. 3v. One output occurs each systick isr, so the sine wave output will be 32khz/256 = 125 hz. (3) part c) a dac has a range of 0 to 3v and needs a resolution of 1mv. In other words, what is the smallest number of dac bits that would satisfy the requirements? precision is (3-0)/0. 001 = 3000 alternatives. 11 bits would only be 2048 alternatives, so we need to use.
