Textbook Notes (280,000)
US (110,000)
LSU (20,000)
EE (300)
EE 2731 (60)
All (60)
Chapter

Experiment 3


Department
Electrical Engineering
Course Code
EE 2731
Professor
All

This preview shows pages 1-3. to view the full 20 pages of the document.
Experiment 3 - Programming the Digilent Spartan-3E
Board Using Xilinx ISE Design Suite
Programming the Spartan-3E Board
This tutorial will introduce you to the programming of CPLDs – Complex Programmable
Logic Devices and FPGAs - Field programmable Gate arrays, using the ISE software
from Xilinx.
CPLDs and FPGAs are different than traditional ICs, due to the fact they are
reconfigurable devices, i.e. their internal interconnections between gates are
reprogrammable. You will learn how to use the ISE Suite to reprogram these internal
connections so as to create a circuit that will behave in a way your design intends it to
behave. Xilinx ISE 14.2 is the design tool you will be using for this purpose, but Xilinx
also makes a free version of this tool, called the Webpack, which you should download
and install on your computer so that you may practice creating and simulating your own
design at home. This experiment will require the Spartan-3E board available for your
use in the laboratory and in the Computer room at 126 EE Bldg. If you desire to
purchase a board of your own, there are many versions available, some starting as low
as $23.00.
Some of the ICs on the boards you will be using are very sensitive to electrostatic
discharge, so please avoid putting your fingers on the chips, as not to damage them.
Also do not remove or change the jumpers on the board. Your cooperation on this
matter is very much appreciated.
Designing a circuit to be programmed onto a CPLD or FPGA will involve 4 steps:
1. Design – The description of the circuit created by using schematic capture or
HDL – Hardware Descriptor Language code, or other means. This step also
involves the simulation of your design, to check its correctness.
2. Synthesis – The generation of the EDIF – Electronic Data Interchange Format
file. In this step all files are checked for proper syntax and they are combined
into a single file using the EDIF format.
3. Place & Route – The information from the EDIF file is used to finalize the layout
of the circuit you designed and an NCD – Native Circuit Description file is made
ready to be used in the programming of the CPLD or FPGA.
4. Program – The CPLD or the FPGA is programmed with the circuit you designed
through the use of programming (.bit) files.
Objective
Learn to program a CPLD or FPGA.
Procedure

Only pages 1-3 are available for preview. Some parts have been intentionally blurred.

Part 1
A full adder is a circuit that adds three one bit inputs, X, Y, and CIN and generates two
outputs COUT and SUM. The truth table and Boolean equations defining the behavior
of this circuit are given below:
X
Y CIN COUT SUM
00000
00101
01001
01110
10001
10110
11010
11111
CINYXSUM
CINYCINXYXCOUT
The following steps will guide you through the design, simulation, synthesis, place and
route, and programming of the CPLD. After executing these steps you will be able to
use the CPLD to add three one bit inputs which generates a two bits result. Some board
switches, SW1, SW2 and SW3, and LEDs, LED1 and LED2, will be used for input and
output respectively.
Starting the ISE Software
Open the Xilinx ISE Project Navigator from the start menu
Start All Programs Xilinx Design Tools ISE Design Suite 14.2 ISE
Design Tools 32 bit or 64 bit Project Navigator
or by double clicking the desktop icon.
Creating a New Project
Select File New Project from project navigator, then, name the project “Exp_6a”.
When naming your own projects, avoid using spaces in the project name as they are
not allowed. Place the project at Z:\Exp_6a. If you save the experiment to the hard

Only pages 1-3 are available for preview. Some parts have been intentionally blurred.

drive of the computer you are using and you do not delete it after you finish working on
it, someone else will have access to it and he/she may copy it. The responsibility of
ensuring that your programs are not used by others is yours. The policy of this
laboratory regarding plagiarism abides by University rules, which requires teachers and
instructors to send the student’s assignment to the Dean of Students. Make sure you
save your work on a flash then delete your work from the main drive. Placing the project
at a different location is as easy as typing the file path into Project Location or by
searching for the location through the use of the Three-dotted Browse button. The
location of the project can always be seen on the top of the Project Navigator screen.
Select HDL for top-level source type.
Note: The address shown in the picture above is not the one you will save your project
to.
You're Reading a Preview

Unlock to view full version