EE 2731 Chapter : E5G56
Document Summary
Equations: f = a"b"c"d + abc"d" + a"bc"d + ab"c"d + a"b"cd + abcd. G = ac"d" + a"c"d + acd + a"cd". // additional comments: module exp_5a(a,b,c,d,f,g); input a,b,c,d; output reg f,g; always @(a,b,c, d) case ({a,b,c}) 3"b111:f = d; endcase always @(a,b,c,d) case ({a,b,c}) // verilog test fixture created by ise for module: exp_5a. #100; //wait for 100 * 1ns = 100ns if ({a, b, c, d} === 4"b1111) endmodule begin. {a, b, c, d} = {a, b, c, d} + 1; end end. // additional comments: module exp_5b(a,b,c,d,f,g); reg [15:0] y; output f,g; always @(a,b,c,d) case ({a,b,c,d}) input a,b,c,d; 4"b0000 : y <= 16"b0000000000000001; assign f = y[0]|y[3]|y[5]|y[6]|y[9]|y[10]|y[12]|y[15]; assign g = y[1]|y[2]|y[5]|y[6]|y[8]|y[11]|y[12]|y[15]; 4"b1111 : y <= 16"b1000000000000000; default : y <= 16"b0000000000000000; endcase endmodule. // verilog test fixture created by ise for module: exp_5b. // inputs reg a; reg b; reg c; reg d;
