EE 2731 Chapter : Lab Report 8
Document Summary
Experiment 8 design of finite state machines. Digital input(s): data inputs : x, clk, restetn. // additional comments: module exp_8a( input x, input clock, output z, input resetn. Endmodule reg [2:1] y=0; parameter [2:1] a = 2"b00, b = 2"b01, c = 2"b10, d = 2"b11; // define the sequential block always @(negedge resetn, posedge clock) assign z = (y == d); //got 101 if (resetn == 0) y <= a; else case (y) A: if (x) y <= b; else y <= a; B: if (x) y <= b; //got 1 else y <= c; C: if (x) y <= d; //got 10 else y <= a; D: if(x) y <=b; else y <=c; default: y <= 2"bxx; endcase. // inputs reg x; reg clock; reg resetn; Digital input(s): data inputs: x, clk, resetn. // define the sequential block always @(negedge resetn, posedge clock) // define output assign z = (y == d);
