EE 2731 Chapter : L R 4
Document Summary
Digital input(s): data inputs: s, r from switches, select lines: none, clock: c. Digital input(s): data inputs: d from switches, select lines: none, clock: c. When the clock is zero, the latch will maintain its existing state. When the clock changes to 1 it follows the behavior in the truth table. When s and r are both equal to 1 and the clock goes from 1 to 0, it will cause an oscillatory behavior. The d latch does not have this problem when s and r are both equal to one. When the clock is equal to one, the output q follows d. when the clock equals zero, q maintains its state until the clock changes back to 1 and then it begins to follow d again. Digital input(s): data inputs: j, k from switches, select lines: none, clock: c. For the d latch, q follows d as long as the clock is 1.
