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Implement the following multiple output combinational logic circuit using a 4 line to
16-line decoder: F1= ∑m (0, 1, 4, 7, 12, 14, 15) F3= ∑m (2, 3, 7, 8, 10)
F2= ∑m (1, 3, 6, 9, 12) F4= ∑m (1, 3, 5)
