COMP 228 Lecture Notes - Lecture 6: Superscalar Processor, Computer Architecture, Basic Block
14 Feb 2017
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Lecture 6 computer organization and design dkp/winter 2017. In the ideal case, we saw that, after pipelining, the instruction-execution bandwidth was _multiplied_ by the number of datapath stages, compared to the instruction-execution bandwidth of a nonpipelined datapath. Our first thought is, let"s have more stages! Consider that the time taken by a stage is the sum of the time for the stage combinational logic plus the time (say, "tau") for the latching of results. "t" is the instruction latency, "t/d" is the stage combinational latency, and "tau" is the per-stage latch overhead. "t/d + tau", and "tau/(t/d + tau)" is the fraction of the stage time consumed by latching overhead. "t/d"---by increasing the number of stages---eventually makes the overhead unbearably large. (this is somewhat similar to amdahl"s law, where one portion speeds up and the other portion doesn"t, resulting in a diminished overall speedup). As relative latch overhead increases, we get less than ideal speedup.
