COMPENG 2DI4 Lecture 35: Lecture Week 10.pdf
12 Feb 2015
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Down counter: design a mod-n up/down counter using jk, extend design to become a base-4 counter with more than one digit. Note: during lecture this example demonstrated an odd double decrement behaviour. This appears to be a timing error in software or the result of a 0 delay example. This circuit and the process used to create it were successfully veri ed in lab using quartus ii. We solved the timing issue by examining the pulse timing and then employing inversion with demorgan. Other ways? another state machine feed second digit with 1/4 clock. Timer state diagram: we already designed one, in week 9 lectures we created a 4 state counter, what distinguishes a timer from a counter, period of the clock pulse. No, but it will demonstrate how to design a timed controller with multipurpose circuits. Return to step 4 and using the ff excitation table, derive the inputs, outputs, and next states.
