COMPENG 2DI4 Lecture 30: Tutorial--6.pdf
12 Feb 2015
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Agenda: lab 3 notes, clock edges, state diagram, state table, analyzing sequential circuits. Clock edges: called it the enable signal before, in digital systems it is desirable to allow the changes in our circuit blocks only at well defined time intervals, this control signal is called the clock. Output depends on input values as well as past behaviour. Built using combinational circuits and flip flops. Over time the circuit changes through a sequence of states as a result of input changes. 0: not a truth table, strictly shows the next state when inputs applied. Includes no information on the present state of the circuit. Includes input, present state and next state of the circuit. Indicates all transitions form each present state to the next state for different values of the input signal: not an easy to understand description of the circuit behaviour. State diagrams: state diagrams are a visual representation of a state table, include inputs, states and outputs.
