COE 758 Lecture 4: COE758L4

• School: Ryerson University
• Department: Computer Engineering
• Course: COE 758
• Professor: Nagi Mekhiel

Document Summary

Multilevel cache system l2 is a way of fixing this issue. T = thit + m1 * tl2hit + m1* m2(tm+block size/bw) Write on a miss, use a write buffer. No need to wait for slow memory, the cost of this is another buffer. Prefetch references ahead of time based on prediction. (can be hardware or software) When a memory stall occurs, out of order execution. Limited physical memory space (main memory dram) that is needed to be used by multiple jobs. Memory allocation: where each job maps to the physical memory (dram) Need to use an algorithm to schedule the jobs to allocated spaces (require a scheduler) How to know which job to get rid of. Back then we had overlays: programmer must divide the program into parts that execute at different time. Protection: using 2 limit registers: low address (base register) and highest address (limit) Job replacement - which job to get rid of.