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Improving cache miss rate:1.
Associative cache deals with conflict misses
Multilevel cache system L2 is a way of fixing this issue
T = Thit + M1 * TL2Hit + M1* M2(Tm+Block size/BW)
Write on a miss, use a write buffer3.
No need to wait for slow memory, the cost of this is another buffer
Prefetch references ahead of time based on prediction. (can be hardware or software)4.
Non blocking cache, superscalaer5.
When a memory stall occurs, out of order execution
Supply to processor critical word first6.
Need memory management:
Memory allocation: where each job maps to the physical memory (DRAM)1.
Need to use an algorithm to schedule the jobs to allocated spaces (require a scheduler)2.
Displacement or swap jobs based on algorithm. How to know which job to get rid of3.
Limited physical memory space (Main memory DRAM) That is needed to be used by multiple jobs
Back then we had Overlays: programmer must divide the program into
parts that execute at different time
Scheduling FCFS, best fit(First come first serve)1.
Size 5k,2k, 3k, 7k, 7k
Memory: 3 partitions. (1k, 6k, 12k)
Protection: using 2 limit registers: low address (base register) and highest address (limit)2.
Job replacement - which job to get rid of3.
Use least recently used, LRU
First in first out
4 - if size of job is > than the allocated space, then we have external fragmentation
Compaction: move all the holes to one end
If size of job < allocated space - Internal Fragmentation then
Illusion for processor to hold all the space it needs
Low cost of large space offered by the hardware system
If the address is 32 bits --> The space it has to access is 2^32 = 4G
Monday, 1 October 2018 09:09 AM
Lectures Page 1