DEPARTMENT OF COMPUTER SCIENCE
CPS310 – COMPUTER ORGANIZATION II
Lab # 1
You are to construct, test, and simulate a 4‐bit section of a CPU as shown in Figure 1.
Note: Multimedia Logic is considered for the simulation and is available at: www.softronix.com
A B R0 R0 out
ADD R1 in
R1 R1 out
Figure 1: 4‐bit section of a CPU architecture.
Figure 1 omits a lot of details, including almost all the control signals. You are required to
determine these control signals as well as the data lines shown. In a real CPU, instruction‐
decoding circuitry would normally be used to generate the control signals automatically. To
simplify this lab, however, you should generate all of the control signals on/off switches
controlled manually. Also employ the followings for monitoring and providing inputs to the BUS
• Hex Keypad to provide data from 0 to F to the BUS lines.
• 8‐segment LED displays to monitor the input/output values in/from all registers in your
Steps in building and testing the design:
ALU design: For the ALU, implement only the arithmetic ADD and the Boolean XOR
operations. Begin your circuit construction by building, testing and debugging the ALU
section first. Use switches to simulate the inputs coming from the BUS and the Y
Note: You can also use the built‐in ALU available from Multimedia Logic library.
Hint: Multimedia Logic provides the design of an ALU called “ALU.LGI” under: