ECE216H1 Lecture Notes - Lecture 33: Chief Operating Officer
19 Apr 2019
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continuing.cat ectueoncqchearem
Acache is asmall fast memory SRAM
Example
Aron fetches an instruction word from address A
The cache controller reads aBlock of successive words
from memory including the word at address Aand stores
the word in the caches memory
It returns the requested instr word to the processor
Now ARMfetches the next instruction at word address Atl
The cache can immediately provide foe word to ARM
As long as ARM fetches instruction words in thecache block
then it is provided bythe cache and called ahit
mIf the requested word is not In the cache it is called
amiss cache controller reads another block from memory
aWhy is this useful
A1cache memory is fast takes l2ARM cycles
The DDR is SLOW takes up to COO ARM cycles
2program code exhibits locality
Loop inst
inst
iadjacent instwords
inst reused repeatedly
BLoop
spacial locality
Temporal laccality
Acache memory is organized into rowsofcolumns
Each row is called acache unecorblock and each
column in acone stores aword
Document Summary
A cache is a small fast memory sram. Aron fetches an instruction word from address a. Block of successive words addressa and stores including the word at a reads controller. Now arm fetches the next instruction the caches memory returns the requested instr word to the processor at word address atl. The cache can immediately provide foe word to arm. As long as then it is provided bythe cache and called a hit m if the requested word is not. In the cache it is called a miss cache controller reads another block from memory awhy is. A 1 cache memory is fast this useful. The ddr is slow takes up to coo arm cycles takes l 2 arm cycles. Loop inst inst i adjacent instwords reused repeatedly inst. Each row is called a cache unecorblock and each column in a cone stores a word. This is an example of direct mapped cache.
