ENVS 1000 Lecture Notes - Lecture 4: Execution Unit, Instruction Set, Central Processing Unit
10 May 2018
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ENVS 1000 Tutorial 4 Notes – Pipeline Correction
Introduction
• Given a different name to emphasize that there are a number of instructions in the
pipeline simultaneously.
• There is a bus interface unit that provides the logic and memory registers necessary to
address memory over the bus.
• Once an instruction is fetched, it is held in a buffer until it can be decoded and executed.
• The number of instructions held will depend upon the size of each instruction, the width
of the memory bus and memory data register, and the size of the buffer.
• As instructions are executed, the fetch unit takes advantage of time when the bus is not
otherwise being used and attempts to keep the buffer filled with instructions.
• In general, modern memory buses are wide enough and fast enough that they do not
limit instruction retrieval.
• Recall that we showed that register-to-register operations could be implemented with
only a single memory access, in the fetch portion of the fetch-execute cycle.
• Fetching the instructions in advance allows the execution of these instructions to take
place quickly, without the delay required to access memory.
• Instructions in the fetch unit buffer are sent to the instruction decoder unit.
• The decoder unit identifies the op code.
• From the op code it determines the type of the instruction.
• If the instruction set is made up of variable length instructions, it also determines the
length of the particular instruction.
• The decoder then assembles the complete instruction with its operands, ready for
execution.
• The execution unit contains the arithmetic/logic unit and the portion of the control unit
that identifies and controls the steps that comprise the execution part for each different
instruction.
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