MGMT 1040 Lecture Notes - Lecture 22: Scalar Processor, Superscalar Processor, Instruction Set

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MGMT 1040 Lecture 22 Notes Execute Cycle
Introduction
An instruction fetch-execute cycle that requires six clock cycles from start to finish will
require six clock cycles whether instructions are performed one at a time or pipelined in
parallel with a dozen other instructions.
It is the average instruction cycle time that is improved by performing some form of
parallel execution.
If an individual instruction must be completed for any reason before another can be
executed, the CPU must stall for the full cycle time of the first instruction.
The difference between scalar and superscalar processing with pipelining in the
execution unit.
In the illustration the execution phase of the fetch-execute cycle is divided into three
parts that can be executed separately.
Thus, the diagram is divided into steps that fetch, decode, execute, and write back the
results of the execute operation.
Presumably, each step is carried out by a separate component within the execution unit.
To simplify the illustration, we have also assumed that in each case the pipeline is full.
Generally, a single fetch unit pipeline is sufficient to fetch multiple instructions, even
when multiple execution units are present.
In the scalar processor, each step is assumed to take one clock cycle.
If the instructions are all of the same length, they will finish consecutively, as shown in
the diagram.
More complexity in the instruction set will create bubbles in the pipeline.
Does not alter the basic idea that we are illustrating.
Panel b of the figure assumes the presence of two execution units.
It also assumes that the instructions executing in parallel are independent of each other
That is, the execution of one does not depend upon results from the other.
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