MGMT 1040 Lecture Notes - Lecture 38: Execution Unit, Itanium, Memory Management Unit
8 May 2018
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MGMT 1040 Lecture 38 Notes – PC Processors
Introduction
• The design shown in this diagram is very similar to the one used in Sun SPARC and IBM
Power and PowerPC processors and, with minor variations, to that used in various
generations of the Intel Pentium and Itanium families, as well as various IBM mainframe
processors.
• As you would expect, the CPU is organized into modules that reflect the superscalar,
pipelined nature of the architecture.
• Although it is difficult to identify the familiar components that we introduced the
control unit, arithmetic/logic unit, program counter, and the like, they are indeed
embedded into the design, as you saw.
• The control unit operation is distributed through much of the diagram, controlling each
step of the usual fetch-execute cycle as instructions flow through different blocks in the
CPU.
• The functions of the arithmetic/logic unit are found within the integer unit.
• The program counter is part of the instruction unit.
• In operation, instructions are fetched from memory by the memory management unit
as they are needed for execution, and placed into a pipeline within the instruction unit.
• The instructions are also partially decoded within the instruction unit, to determine the
type of instruction that is being executed.
• This allows branch instructions to be passed quickly to the branch processing unit for
analysis of future instruction flow.
• Instructions are actually executed in one of several types of execution units.
• Each execution unit has a pipeline designed to optimize the steps of the execute cycle
for a particular type of instruction.
• As you can see from the block diagram, there are separate execution units for branch
instructions, for integer instructions, for floating point instructions, and for load and
store instructions.
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