COMPSCI 61C Lecture Notes - Lecture 19: Datapath, Control Logic, Combinational Logic
28 Aug 2017
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Flip- ops (ffs) and combinational logic have some delays. Gates: delay from input change to output change. Signals at ff d input must be stable before active clock edge to allow signal to travel within the ff (set-up time), and we have the usual clock-to-q delay. Register-register timing: one complete cycle (add / sub) Clock starts, and the program counter is updated. Control logic, and in parallel, the register le reads rs, rt. Add two registers and branch if result 0 (this one!) * lw rt, rs, o set #rs incremented by o set after load. * this would only work if it were a store. Stage 1: analyze instruction set to determine datapath requirements. Meaning of each instruction given by register transfers. Datapath must include storage element for isa registers. Stage 2: select set of datapath componenets & establish clock methodology. Stage 3: assemble datapath components that meet the requirements.
