COMPSCI 61C Lecture Notes - Lecture 17: Datapath, Synchronous Circuit, Critical Path Method

• School: Berkeley
• Department: Computer Science
• Course: COMPSCI 61C
• Professor: Gerald Friedland

Document Summary

The critical path is the slowest path through the circuit. For a synchronous circuit, the clock cycle must be longer than the critical path. The critical path is the combination of the clk->q time for the ip op, the combinational delay, and the setup time. Clk->q: time it takes from when the clock edge comes to the ip- op output changes. Combinational delay: the slowest/longest path in the combinational logic. Setup time: time that the ip- op requires the the input be stable before the clock comes. They don"t like their input changing before the clock comes (setup time) They don"t like their input changing just after the clock edge (hold time) Hold time violations occur when there exists a path through the circuit that is very short. Clk->q + shortest combinational delay < hold time [note: test q] How a d-type flip-flop works [not on test] A latch passes d->q when c is high.