CS/IS 101 Lecture Notes - Lecture 3: Circuit Diagram, Lga 1151, Microarchitecture
Document Summary
Cpu cache: sram -> small bits of ram that"s put on the cpu so that it can always process data and pipeline stalls doesn"t occur. Level 1 cache -> 64k of ram. Runs at the multiplied speed of the cpu. Level 2 cache -> feeds the level 1 cache. Level 3 (l3) cache -> megabyte sized. Set association: defines how the different types of caches are efficient at being able to faster than ram. Usually what prevents a pipeline stall multiplied speed hand the right piece of code up to the cpu itself (not in the a+ cert exam) Amd believe in big caches, intel believes in smart, but low caches. Cpu caching works between ram and the cpu. Cpu socket: the shape, pins, and form of the cpu. Also the actual socket that the cpu fits in. Microarchitecture: the circuit diagram on the inside of the cpu. Socket names: pin grid array (pga), land grind array (lga)
