ECE327 Final: ECE 327 University of Waterloo 2017 Term 1 Final

• School: University of Waterloo
• Department: Electrical and Computer Engineering
• Course: ECE327
• Professor: All

Document Summary

Instructions and general information: 100 marks total, time limit: 2. 5 hours (150 minutes, no books, no notes, no computers. If you are confused about a question, write down your assumptions or interpretation: justi cations of answers will be marked according to correctness, clarity, and concision. F) + ( a v ish f) + (v il) Q1 (5 marks) vhdl semantics (estimated time: 10 minutes) For full marks, you must justify your answer in terms of the vhdl semantics. Q2 (15 marks) area analysis (estimated time: 25 minutes) Calculate the minimum number of fpga cells required to implement the vhdl code below. <= b + c; end process; diff ab_lt_bc z. Q3 (20 marks) performance (estimated time: 25 minutes) You work for blueberry solutions, a leading innovator in hardware system design. Your cousin just completed an ipo of her software company and used some of the money to purchase blueberry solutions.