ECE327 Midterm: ECE 327 University of Waterloo 2016 Term 2 Midterm

• School: University of Waterloo
• Department: Electrical and Computer Engineering
• Course: ECE327
• Professor: All

Document Summary

Instructions and general information: 100 marks total, time limit: 1 hour and 20 minutes (80 minutes, no books, no notes, no computers. If you are confused about a question, write down your assumptions or interpretation: justi cations of answers will be marked according to correctness, clarity, and concision. Q1 (25 marks) vhdl (estimated time: 15 minutes) On the rst day of your dream co-op job at amabagookify, the company goes bankrupt and you lose your job. You decide to create a startup company based on your idea for a new hardware description language, why wait? , abbreviated as yw . To get the company going quickly, you decide to base yw on vhdl, but eliminate wait statements and sensitivity lists, because they are too complicated. So far, you have decided that in each simulation cycle: each process is executed exactly once, the processes are executed in the order in which they appear in the architecture.