EECE 353 Assignment 1 Q2.pdf

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Department
Electrical and Computer Engineering
Course
EECE 252
Professor
lemieux,guy
Semester
Fall

Description
library ieee; useieee.std_logic_1164.all; useieee.std_logic_arith.all; Entity DECODER3IN8OUTis Port( input : in std_logic_vector( 2downto 0); output : out std_logic_vector( 7downto 0) ); End DECODER3IN8OUT; Architecture behavioural of DECODER3IN8OUTis begin process( input) begin case input is when "000" =>output <="00000001";
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