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MGMT 1050 Study Guide - Fall 2018, Comprehensive Midterm Notes - Mgmt, Central Processing Unit, Computer Data StoragePremium

163 pages88 viewsFall 2018

Department
Management
Course Code
MGMT 1050
Professor
Babar Khan
Study Guide
Midterm

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MGMT 1050
MIDTERM EXAM
STUDY GUIDE
Fall 2018

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MGMT 1050 Lecture 1 Notes Memory in the Data
Introduction
Once this has occurred, the data is in memory, ready for the program to use.
This technique of I/Omemory data transfer is known as direct memory access, or more
commonly, simply as DMA.
In Little Man terms, direct memory access could be viewed as providing data for the
Little Man by loading data directly into the mailboxes through a rear door, bypassing the
Little Man I/O instruction procedures.
To reemphasize the fact that this operation only takes place under program control, we
would have to provide a means for the Little Man to initiate such a transfer and a means
to notify the Little Man when the data transfer is complete.
For direct memory access to take place, three primary conditions must be met
There must be a method to connect together the I/O interface and memory.
In some systems both are already connected to the same bus, so this requirement is
easily met.
In other cases, the design must contain provisions for interconnecting the two.
The issue of system configuration is discussed
The I/O module associated with the particular device must be capable of reading and
writing to memory.
It does so y siulatig the CPU’s iterfae with eory.
Specifically, the I/O module must be able to load a memory address register and to read
and write to a memory data register, whether its own or one outside the I/O module.
There must be a means to avoid conflict between the CPU and the I/O module.
It is not possible for the CPU and a module that is controlling disk I/O to load different
addresses into the MAR at the same instant.
For example, nor is it possible for two different I/O modules to transfer data between
I/O and memory on the same bus at the same instant.
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This requirement simply means that memory can only be used by one device at a time,
although
As we mentioned, some systems interleave memory in such a way that the CPU and I/O
modules can access different parts of memory simultaneously.
Memory data transfer is known as direct memory access, or more commonly, simply as
DMA.
In Little Man terms, direct memory access could be viewed as providing data for the
Little Man by loading data directly into the mailboxes through a rear door, bypassing the
Little Man I/O instruction procedures.
To reemphasize the fact that this operation only takes place under program control, we
would have to provide a means for the Little Man to initiate such a transfer and a means
to notify the Little Man when the data transfer is complete.
For direct memory access to take place, three primary conditions must be met
There must be a method to connect together the I/O interface and memory.
In some systems both are already connected to the same bus, so this requirement is
easily met.
In other cases, the design must contain provisions for interconnecting the two.
The issue of system configuration is discussed
The I/O module associated with the particular device must be capable of reading and
writing to memory.
It does so y siulatig the CPU’s iterfae with eory.
Specifically, the I/O module must be able to load a memory address register and to read
and write to a memory data register, whether its own or one outside the I/O module.
There must be a means to avoid conflict between the CPU and the I/O module.
find more resources at oneclass.com
find more resources at oneclass.com
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