MGMT 1050 Chapter Notes - Chapter 7: Von Neumann Architecture, Opcode
MGMT 1050 Chapter 7 Notes – Summary
Introduction
• Interconnections between various parts of a computer are provided by buses.
• There are many different types of buses. Buses connect different modules within the
CPU.
• They also connect the CPU to memory and to the I/O peripherals.
• Buses can connect two components in a point-to-point configuration or may
interconnect several modules in a multipoint configuration.
• Buses may be parallel or serial.
• In general, the lines on buses carry signals that represent data, address, and control
functions.
• Instructions fall naturally into a small number of categories
• Moves, integer arithmetic, floating point arithmetic, data flow control, and so forth.
• There are also privileged instructions, which control functions internal to the CPU and
are accessible only to the operating system.
• Instructions in a real CPU are made up of an op code and up to three address field
operands.
• The size of the instruction word is CPU dependent.
• Some computers use variable length instruction words. Other computers use a fixed
length instruction, most commonly, 32 bits in length.
• There are many excellent textbooks that describe the implementation and operation of
the components of the computer system.
• A brief, but very clear, explanation of the fetch-execute cycle can be found in Davis and
Rajkumar [DAV02].
• Three classic engineering textbooks that discuss the topics in great detail are those
authored by Stallings [STAL05], Patterson and Hennessy [PATT07], and Tanenbaum
[TAN05].
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