MGMT 1050 Chapter Notes - Chapter 3: Computer Memory, Instruction Set, Opcode
MGMT 1050 Chapter 3 Notes – Summary
Introduction
• The size of the instruction word, in bits, is dependent on the particular CPU architecture,
particularly by the design of its instruction set.
• The size of the instruction word may be fixed at, say, 32 bits.
• It may vary depending on the usage of the address fields.
• The Sun Sparc CPU, for example, takes the former approach.
• Every instruction word is exactly 32 bits wide.
• Conversely, some of the basic instruction words for the x86 microprocessor line used in
the common PC, for example, are as small as 1 or 2 bytes long.
• There are some instructions in the Pentium microprocessor that are as many as 15 bytes
long.
• The IBM Series z architecture is an evolutionary extension of upward compatible CPU
architectures dating back to the 1960s.
• The legacy instructions in the IBM Series z CPU are mostly 4 bytes, or 32 bits long, with a
few 2-byte or 6-byte long instructions.
• To expand the architecture to 64-bit addressing and data, IBM added a number of new
instructions.
• These are all 6 bytes in length.
• The challenge in establishing an instruction word size is the need to provide both
enough op code bits to support a reasonable set of different instructions.
• As well as enough address field bits to meet the ever growing demand for increasing
amounts of addressable memory.
• Consider again, for example, the extremely straightforward instruction format shown.
• This format assumes a single address field with a 32-bit fixed length instruction.
• With the division shown, we have access to 28 = 256 different instructions and 224 =
approximately 16 million memory addresses.
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