EE 2731 Chapter : Lab Report 7
Document Summary
Design of finite state machines using cad tools. Encoding a fsm using verilog and isd development kit to detect the sequence 101. // additional comments: module exp_8a( input clock, input reset, input w, output z. // define the sequential block reg [2:0] y; parameter [2:0] a = 3"b000, b = 3"b001, c = 3"b010, d = 3"b100; if (reset==0) y <= a; else begin end case (y) endcase assign z = (y==d); D: if (w) y<=b; else y<=c; default: y<=3"bxxx; always @(negedge reset, negedge clock) begin end. // verilog test fixture created by ise for module: exp_8a. // add stimulus here module exp_8a_tb; reg clock, reset, w; wire z; reg[15:0] sequence; integer i; Exp_8a dut( clock, reset, w, z); initial begin. // additional comments: reg [2:1] y; parameter [2:1] a = 2"b00, b = 2"b01, c = 2"b10, d = 2"b11; assign z = (y == d);
