CEG 3136 Lecture Notes - Lecture 2: Status Register, Processor Register, Operand

• School: University of Ottawa
• Department: Computer Engineering
• Course: CEG 3136
• Professor: Basim Hafidh

Document Summary

Module 2 cpu register, condition codes, and addressing modes. Used for temporary data storage, parameter and control information storage for subroutines, and general data storage: notation used in comments, register name. Indicates a register and its contents: right arrow indicated data transfer operation indicates an exchange of data, contents of memory () b means that the contents of memory location are transferred to b. The content of a is then stored at the address the sp points to: pula, accumulator a is loaded from the address indicated by the sp. The sp is ten incremented by one: subroutine instruction, jsr address, sets up conditions to return to normal program flow, then transfer control to a subroutine. Uses the address of the instruction following the jsr as a return address: decrements the sp by two to allow the two bytes of the return address to be stacked, stacks the return address.