MGMT 1000 Chapter Notes - Chapter 10: Memory Buffer Register, Memory Address Register, Memory Address
MGMT 1000 Chapter 10 Notes – Summary
Introduction
• Retrieved from the memory location currently addressed by the memory address
register.
• The last two registers will be discussed in more detail, when we explain the workings of
memory.
• Although the memory address register and memory data register are part of the CPU,
operationally these two registers are more closely associated with memory itself.
• The control unit will also contain several 1-bit registers, sometimes known as flags that
are used.
• To allow the computer to keep track of special conditions such as arithmetic carry and
overflow, power failure, and internal computer error.
• Usually, several flags are grouped into one or more status registers.
• In addition, our typical CPU will contain an I/O interface that will handle input and
output data as it passes between the CPU and various input and output devices, much
like the LMC in and out baskets.
• For simplification, we will view the I/O interface as a pair of I/O registers, one to hold an
I/O address that addresses a particular I/O device, the other to hold the I/O data.
• These registers operate similarly to the memory address and data registers.
• Later, we will discuss a more common way of handling I/O that uses memory as an
intermediate storage location for I/O data.
• Most instructions are executed by the sequenced movement of data between the
different registers in the ALU and the CU.
• Each instruction has its own sequence.
• Most registers support four primary types of operations
• Registers can be loaded with values from other locations, in particular from other
registers or from memory locations.
• This operation destroys the previous value stored in the destination register
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