MGMT 1050 Chapter Notes - Chapter 5: Processor Register, Instruction Set, Memory Address
MGMT 1050 Chapter 5 Notes – Summary
Introduction
• Nearly all new CPU designs use fixed length instructions exclusively.
• As we mentioned previously in our discussion of memory size, an effective alternative to
large instructions or variable instruction words is to store the address that would
otherwise be located in an instruction word address field at some special location that
can hold a large address
• Such as a general purpose register, and use a small address field within the instruction
to point to the register location.
• There are a number of variations on this theme.
• This technique is used, even on systems that provide variable length instructions.
• A single CPU might provide a number of different variations to increase the flexibility of
the instruction set.
• This flexibility also includes the ability to code programs that process lists of data more
efficiently.
• The various ways of addressing registers and memory are known as addressing modes.
• The Little Man Computer provides only a single mode, known as direct addressing.
• The alternative just described is called register deferred addressing.
• An example of a deferred LOAD instruction is shown.
• This instruction would load the data value stored at memory address 3BD421 into
general purpose register 7.
• There are a number of addressing modes discussed in detail in Supplementary
• The use of different addressing modes is the most important method for minimizing the
size of instruction words and for writing efficient programs.
• Examples of instruction formats from two different CPUs are shown
• There may be several different formats within a single CPU.
• We have shown only a partial set for each machine, although the SPARC set is complete
except for small variations.
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